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Available in 2012

Callaghan CampusSemester 2
UoN SingaporeTrimester 1

Previously offered in 2013, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004

Introduces students to the principles and practices of digital logic design using programmable logic devices and CAD tools. Topics include programmable logic devices and structures, design tools, VHDL hardware description language, datapath design, control-unit design.

Objectives
* To further expose students to the various aspects of digital design practices using programmable logic devices (PLDs).
* To gain more working knowledge of CAD tools available for digital design
* To present a complete treatment of VHDL
* To introduce students to the architecture and design of modern computers
* To solidify the computer architecture theory and digital design practices through project work
* To gain further experience in group learning through project work
Content
* Programmable Logic Devices
* Altera's design tools
* Computer Architecture and Performances
* MIPS Instruction Set Architecture
* Arithmetic for Computers
* The Processor: Datapath and Control
* VHDL
* Project involving the design of an embedded microcontroller
Replacing Course(s)
NA
Transition
NA
Industrial Experience
0
Assumed Knowledge
ELEC2700
Modes of Delivery
Internal Mode
Teaching Methods
Lecture
Practical
Tutorial
Assessment Items
Examination: Formal
Final Exam - As per the University's exam timetable and course handout
Projects
Design projects as per course handout.

PSB students please note: The project represents a major assessment item in this course. Course material is rearranged for part-time evening students in UoN Singapore (block mode) so that lecture material is presented in the early weeks of the course and the latter weeks primarily focus on project work. On-going access to lecture / tutorial staff is maintained during the project period through scheduled help desks / open labs.
Quiz - Class
Class quizzes as per course handout
Contact Hours
Laboratory: for 2 hour(s) per Week for Full Term
Lecture: for 4 hour(s) per Week for Full Term

Timetables